Visible to Intel only — GUID: sam1412661469249
Ixiasoft
ALTDQ_DQS2 Features
ALTDQ_DQS2 Device Support
Resource Utilization and Performance
ALTDQ_DQS2 Parameter Settings
ALTDQ_DQS2 Data Paths
ALTDQ_DQS2 Ports
Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example
Arria V Design Example
IP-Generate Command
ALTDQ_DQS2 IP Core User Guide Archives
Document Revision History
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices
DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices
Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Visible to Intel only — GUID: sam1412661469249
Ixiasoft
ALTDQ_DQS2 Features
The ALTDQ_DQS2 IP core has the following features:
- Access to dynamic on-chip termination (OCT) controls to switch between parallel termination during reads and series termination during writes.
- High-performance support for DDR interface standards.
- 4- to 36-bit programmable DQ group widths.
- Half-rate registers to enable successful data transfers between the I/O registers and the core logic.
- Access to I/O delay chains to fine-tune delays on the data or strobe signals.
- Access to hard read FIFO.
- Access to latency shifter FIFO and data valid FIFO for efficient control of DQS gating and read operations (Arria V and Cyclone V devices only).