DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
The following tables lists the DQS configuration block bit sequence, description, and settings for Arria V GZ and Stratix V devices.
| Legend in I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices | Bit | Bit Name | Description |
|---|---|---|---|
| E |
5..0 |
dqsbusoutdelaysetting |
Connects to the delayctrlin port of the first D4 delay chain. Controls the first D4 delay chain in DQS delay chain path (after the DQS delay chain). This is the delay tuning of the DQS signal feeding into the DQS bus. For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
| F |
11..6 |
dqsbusoutdelaysetting2 |
Connects to the delayctrlin port of the second D4 delay chain. Controls the second D4 delay chain in DQS delay chain path (after the first D4 delay chain). This is the delay tuning of the DQS signal feeding into the DQS bus. For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
| G |
17..12 |
octdelaysetting1 |
Connects to the delayctrlin port of the D5 OCT delay chain. Controls the dynamic OCT output register-to-I/O buffer delay chain (D5). For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
| H |
23..18 |
octdelaysetting2 |
Connects to the delayctrlin port of the second D5 OCT delay chain. Controls the dynamic OCT output register-to-I/O buffer delay chain (second D5). For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
| — |
27..24 |
addrphasesetting addrpowerdown addrphaseinvert |
Unconfigurable bits. Always set bits to its default value. |
| I |
29..28 |
dqsoutputphasesetting |
Connects to the phasectrlin port of the clock phase select (in the DQS output path) to select between phase shifts of 0°, 45°, 90°, and 135°. Use this bit to level the DQS write output. |
| — |
30 |
dqsoutputpowerdown |
Unconfigurable bits. Always set bits to its default value. |
| J |
31 |
dqsoutputphaseinvert |
Connects to the phaseinvertctrl port of the clock phase select (in the DQS output path) to select between the non-inverted and inverted output. This setting allows the phase output from the delay chain to be inverted to gain additional phases. |
| K |
33..32 |
dqoutputphasesetting |
Connects to the phasectrlin port of the clock phase select (in the DQ output path) to select between phase shifts of 0°, 45°, 90°, and 135°. DQ leveling clock select. n Use this bit to level the DQ write output. |
| — |
35..34 |
dqoutputpowerdown |
Unconfigurable bits. Always set bits to its default value. |
| L |
36 |
dqoutputphaseinvert |
Connects to the phaseinvertctrl port of the clock phase select (in the DQ output path) to select between the non-inverted and inverted output. This setting allows the phase output from the delay chain to be inverted to gain additional phases. |
| — |
40..37 |
resyncinputphasesetting resyncinputpowerdown resyncinputphaseinvert |
Unconfigurable bits. Always set bits to its default value. |
| M |
42..41 |
postamblephasesetting |
Connects to the phasectrlin port of the clock phase select (for the DQS enable control block) to select between phase shifts of 0°, 45°, 90°, and 135°. Use this clock phase select block to level the postamble (dqsenablein signal at the DQS enable control block). |
| — |
44..43 |
postamblepowerdown |
Unconfigurable bits. Always set bits to its default value. |
| N |
45 |
postamblephaseinvert |
Connects to the phaseinvertctrl port of the clock phase select (for the DQS enable control block) to select between the non-inverted and inverted output. Use this clock phase select block to level the postamble (dqsenablein signal at the DQS enable control block). This setting allows the phase output from the delay chain to be inverted to gain additional phases. |
| — |
65..46 |
dqs2xoutputphasesetting n dqs2xoutputpowerdown dqs2xoutputphaseinvert dq2xoutputphasesetting dq2xoutputpowerdown dq2xoutputphaseinvert ck2xoutputphasesetting ck2xoutputpowerdown ck2xoutputphaseinvert dqoutputzerophasesetting postamblezerophasesetting postamblepowerdown dividerioehratephaseinvert dividerphaseinvert |
Unconfigurable bits. Always set bits to its default value. |
| O |
68..66 |
enaoctcycledelaysetting |
Connects to the enaoutputcycledelay port of the output alignment block (in the dynamic OCT control path) to allow additional registers to be used. Use this bit to adjust the phase of the write-leveled OCT or output data signal. |
| P |
69 |
enaoctphasetransferreg |
Connects to the enaphasetransferreg port of the output alignment block (in the dynamic OCT control path) to allow an additional negative edge-triggered register to be added to the OCT, output data, or output enable path to satisfy the setup or hold time requirement for the phase transfer. |
| Q |
77..70 |
dqsdisablendelaysetting |
Connects to the delayctrlin port of the T11 delay chain (located between the dqsenableout port of the DQS enable control block and the dqsdisablen port of the DQS delay chain). This is to align post-amble signal in terms of DQS signal by selecting different delays. |
| R |
85..78 |
dqsenabledelaysetting |
Connects to the delayctrlin port of the T11 delay chain (located between the dqsenableout port of the DQS enable control block and the dqsenable port of the DQS delay chain). This is to align post-amble signal in terms of DQS signal by selecting different delays. |
| S |
86 |
enadqsenablephasetransferreg |
Connects to the enaphasetransferreg port of the DQS enable control block to allow an additional negative edge-triggered register to be added to the DQS enable control path to satisfy the setup or hold time requirement for the phase transfer. |
| T |
88..87 |
dqsinputphasesetting |
Connects to the phasectrlin port of the DQS delay chain block. To control the phase selection for the DQS delay chain. The frequency range that this works at is 300 MHz to 800 MHz. |
| U |
89 |
enadqsphasetransferreg |
Connects to the enaphasetransferreg port of the output alignment block (in the DQS output path and OE path) to allow an additional negative edge-triggered register to be used. |
| V |
90 |
enaoutputphasetransferreg |
Connects to the enaphasetransferreg port of the output alignment block (in the DQ output path and OE path) to allow an additional negative edge-triggered register to be added to the output data or output enable path to satisfy the setup or hold time requirement for the phase transfer. |
| W |
93..91 |
enadqscycledelaysetting |
Connects to the enaoutputcycledelay port of the output alignment block (in the DQS output path and OE path) to allow additional registers to be enabled in the output alignment block of the output data or output enable path of a DQS I/O. This is normally used to adjust the phase of the write-leveled OCT or output data signal. |
| X |
96..94 |
enaoutputcycledelaysetting |
Connects to the enaoutputcycledelay port of the output alignment block (in the DQ output path and OE path) to allow additional registers to be enabled in the output alignment block of the output data or output enable path of a DQ I/O. Use this bit to adjust the phase of the write-leveled OCT or output data signal. |
| — |
100..97 |
enainputcycledelaysetting enainputphasetransferreg |
Unconfigurable bits. Always set bits to its default value. |
| Bit | Bit Name | Default Value (Binary) | Min Value | Max Value | Inc. Unit |
|---|---|---|---|---|---|
| 5..0 |
dqsbusoutdelaysetting |
0 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
| 11..6 |
dqsbusoutdelaysetting2 |
0 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
| 17..12 |
octdelaysetting1 |
0 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
| 23..18 |
octdelaysetting2 |
0 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
| 27..24 |
addrphasesetting addrpowerdown addrphaseinvert |
100 |
— |
— |
— |
| 29..28 |
dqsoutputphasesetting |
0 |
00 = 0° 01 = 45° 10 = 90° 11 = 135° |
||
| 30 |
dqsoutputpowerdown |
1 |
— |
||
| 31 |
dqsoutputphaseinvert |
0 |
0 = bypass 1 = enable |
||
| 33..32 |
dqoutputphasesetting |
0 |
00 = 0° 01 = 45° 10 = 90° 11 = 135° |
||
| 35..34 |
dqoutputpowerdown |
10 |
— |
||
| 36 |
dqoutputphaseinvert |
0 |
0 = bypass 1 = enable |
||
| 40..37 |
resyncinputphasesetting resyncinputpowerdown resyncinputphaseinvert |
100 |
— |
||
| 42..41 |
postamblephasesetting |
0 |
00 = 0° 01 = 45° 10 = 90° 11 = 135° |
||
| 44..43 |
postamblepowerdown |
10 |
— |
||
| 45 |
postamblephaseinvert |
0 |
0 = bypass 1 = enable |
||
| 65..46 |
dqs2xoutputphasesetting dqs2xoutputpowerdown dqs2xoutputphaseinvert dq2xoutputphasesetting dq2xoutputpowerdown dq2xoutputphaseinvert ck2xoutputphasesetting ck2xoutputpowerdown ck2xoutputphaseinvert dqoutputzerophasesetting postamblezerophasesetting postamblepowerdown dividerioehratephaseinvert dividerphaseinvert |
0010_0000_1000_1000_0100 |
— |
||
| 68..66 |
enaoctcycledelaysetting |
10 |
000: Not supported 001: Not supported 010: No delay 011: 1 cycle delay 100: 2 cycle delay 101: 3 cycle delay 110: Not supported 111: Not supported |
||
| 69 |
enaoctphasetransferreg |
0 |
0 = bypass 1 = enable |
||
| 77..70 |
dqsdisablendelaysetting |
0 |
intrinsic delay |
3.2 ns + intrinsic delay |
12.5 ps |
| 85..78 |
dqsenabledelaysetting |
0 |
intrinsic delay |
3.2 ns + intrinsic delay |
12.5 ps |
| 86 |
enadqsenablephasetransferreg |
0 |
0 = bypass 1 = enable |
||
| 88..87 |
dqsinputphasesetting |
0 |
00 = 0° 01 = 45° 10 = 90° 11 = 135° |
||
| 89 |
enadqsphasetransferreg |
0 |
0 = bypass 1 = enable |
||
| 90 |
enaoutputphasetransferreg |
0 |
0 = bypass 1 = enable |
||
| 93..91 |
enadqscycledelaysetting |
10 |
000: Not supported 001: Not supported 010: No delay 011: 1 cycle delay 100: 2 cycle delay 101: 3 cycle delay 110: Not supported 111: Not supported |
||
| 96..94 |
enaoutputcycledelaysetting |
10 |
000: Not supported 001: Not supported 010: No delay 011: 1 cycle delay 100: 2 cycle delay 101: 3 cycle delay 110: Not supported 111: Not supported |
||
| 100..97 |
enainputcycledelaysetting enainputphasetransferreg |
0 |
— |
||