ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

DQS Write Operation

The driver asserting the dqs_enable signal at 8.925 ms begins the write operation. This will configure the ALTDQ_DQS2’s output_strobe_ena to high, getting ready to send out strobe to the DQS agent. The dqs_write signal is asserted at 8.935 ms. This sets the write_oe_in signal of the ALTDQ_DQS2 IP core to high, getting ready to send out data to the DQS agent. The data are written to the dqs_writedata of the DQS driver, and then reflected in the dq signal of the ALTDQ_DQS2 IP core. The data written out from the DQS driver is also stored in check_fifo. During the DQS write operation, the strobe_io and agent_dqs_in is toggling. Dqs_write deasserts at 8.985 ms and dqs_enable deasserts at 8.995ms. Outgoing data from the dq signal of the ALTDQ_DQS2 IP core is center-aligned to the strobe (strobe_io).

The following figure shows the DQS write operation waveform.

DQS Write Operation Waveform


Note: Before and after the DQS write operation, the strobe_io signal is in Hi-Z mode.

The following figure shows the waveform for the dynamic configuration simulation generated after executing topwave.do (located in the simulation/modelsim folder). The output_strobe_ena is held high from 8.925 ms to 8.995 ms while the strobe_io signal starts toggling only between 8.94 ms and 9.01 ms. The write_oe_in signal is held high throughout the five sets of valid write_data_in, which is between 8.935 ms and 8.955 ms. Center-aligned output data appears on the read_write_data_io signal between 8.949 ms and 8.999 ms.

DQS Write Operation Waveform After Executing the topwave.do File


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