ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices

Figure 8. I/O and DQS Delay Chains for Arria V and Cyclone V Devices


The following table lists the I/O configuration block bit sequence, description, and settings for Arria V and Cyclone V devices.

Table 6.  I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices

Legend in Figure 8

Bit

External Bit Name

Description

A

4..0

padtoinputregisterdelaysetting

Connects to the delayctrlin port of the D1 delay chain.

Controls the I/O buffer-to-input register delay chain (D1).

Tunes the DQ delay (read calibration) for DDR applications.

For delay values, refer to the “Programmable IOE Delay” sections in the Arria V Device Datasheet and the Cyclone V Device Datasheet, respectively.

B

9..5

outputenabledelaysetting

Connects to the delayctrlin port of the D5 delay chain.

Controls the output register-to-I/O buffer delay chain (D5) in the output enable paths. This delay is used for write calibration for DDR application.

For delay values, refer to the “Programmable IOE Delay” sections in the Arria V Device Datasheet and the Cyclone V Device Datasheet, respectively.

C

14..10

outputregdelaysetting

Connects to the delayctrlin port of the D5 delay chain.

Controls the output register-to-IO Buffer delay chain (D5) in the output path paths. This delay is used for write calibration for DDR application.

For delay values, refer to the “Programmable IOE Delay” sections in the Arria V Device Datasheet and the Cyclone V Device Datasheet, respectively.

D

17..15

readfifomode

Connects to the dynfifomode port of input register read FIFO block. The read FIFO can be configured as a read FIFO or a Unified SerDes Block.

E

19..18

readfiforeadclockselect

Connects to the clksel port of the read FIFO clock select block. This controls the read FIFO Read clock source Select.

F

20

outputhalfratebypass

Sets the multiplexer in the output enable and output data path logic to dynamically bypass the half-rate to full-rate DDIO. Used only with the hard PHY.

—

24..21

Not mapped to any port

Unconfigurable bits. Always set bits to its default value.

Table 7.  I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices

Bit

Bit Name

Default Value (Binary)

Min. Value

Max. Value

Inc. Value

4..0

padtoinputregisterdelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

9..5

outputenabledelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

14..10

outputregdelaysetting

0

intrinsic delay

775 ps + intrinsic delay

25 ps

17..15

readfifomode

0

000: Half-rate Read FIFO Mode

001: Full-rate Read FIFO Mode

010: Deserializer Bit Slip Mode

011: Deserializer with Input from Bit Slip

100: Deserializer with Input from I/O

101: Serializer mode

110: Not supported

111: Not supported

19..18

readfiforeadclockselect

0

00: Select Core CLKIN1

01: Select DQS_CLK (PHY_CLK)

10: Select SEQ_HR_CLK (PHY_CLK)

11: Select VCC (Disabled)

20

outputhalfratebypass

0

0: Engage Half-Rate Register

1: Bypass Half-Rate Register

24..21

Not mapped to any port

0

—

—

—

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