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ALTDQ_DQS2 Features
ALTDQ_DQS2 Device Support
Resource Utilization and Performance
ALTDQ_DQS2 Parameter Settings
ALTDQ_DQS2 Data Paths
ALTDQ_DQS2 Ports
Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example
Arria V Design Example
IP-Generate Command
ALTDQ_DQS2 IP Core User Guide Archives
Document Revision History
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices
DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices
Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
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Instantiating the ALTDQ_DQS2 IP Core
To instantiate the ALTDQ_DQS2 IP core, perform the following steps:
- In the Quartus® Prime software, open the Top_AV_15_1.qar design example and restore the archived file into your working directory.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.
- Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK.
- On the Parameter Settings tab, on the General page, specify the parameters as shown in the following figure. These parameters configure the general settings for the ALTDQD_DQS2 instance.
Figure 27. ALTDQ_DQS2 Parameter Settings for Arria V Devices
- Click Finish.
Note: If your design requires bidirectional strobe, you must set the DQS phase shift to 0 degree to bypass the DQS delay chain.
Related Information