ALTDQ_DQS2 IP Core User Guide

ID 683742
Date 5/08/2017
Public
Document Table of Contents

Blocks in DQ and DQS Data Input Path

The following table lists the blocks in the DQ and DQS input paths.

Blocks in DQ and DQS Input Path
Block Name Description

DQS enable

  • Represents the AND-gate control on the DQS input that grounds the DQS input strobe when the strobe goes to Hi-Z after a DDR read postamble. The DQS enable block enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change.
  • The clock to the hard data valid FIFO must be synchronous with the capture_strobe_in to ensure the DQS enable signal is in-sync with capture_strobe_in.
  • For more information about the DQS enable block, refer to the “Update Enable Circuitry” in the External Memory Interfaces chapter in the respective device handbook.

DQS enable control

  • Represents the circuitry that controls the DQS enable block. A DQS enable control block controls each DQS enable block.
  • For more information about the DQS enable control block, refer to the “DQS Postamble Circuitry” in the External Memory Interfaces chapter in the respective device handbook.

DQS delay chain

  • Represents the delay chains that delay signals.
  • For more information about the DQS delay chain block, refer to “DQS Delay Chain” in the External Memory Interfaces chapter in the respective device handbook.