ALTDQ_DQS2 IP Core User Guide

Download PDF
ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

Dynamic Reconfiguration for ALTDQ_DQS2

When static timing closure is challenging (for example, high frequency, high board trace skew, and high timing uncertainty), dynamically reconfiguring the ALTDQ_DQS2 IP core may provide additional timing margin. Arria V, Cyclone V, and Stratix V devices contain reconfigurable logic, allowing you to adjust the delay of several datapaths at runtime.

The I/O configuration block and the DQS configuration block are shift registers that you can use to dynamically change the settings of various device configuration bits. The shift registers are configured with the rest of the device when the Programmer Object File (.pof). In dynamic mode, you can override the static values at runtime with a scan chain. You can reconfigure the I/Os by turning on the Use dynamic configuration scan chains option.

The following figure shows the Use dynamic configuration scan chains option.

Figure 5. Use Dynamic Configuration Scan Chains Option


The following figure shows the dynamic reconfiguration scan chain implementation.

Figure 6. Reconfiguration Scan Chain


Each I/O contains a scan chain block. The DQS logic also contains its own scan chain block. You can use I/O scan chain blocks to configure DQ and DQS I/O configuration registers (for example, delay chain) and you can use the DQS logic scan chain to configure DQS logic configuration (for example, DQS postamble phase). You can serially scan configuration bits into each scan chain block with the following operating sequence:

The ALTDQ_DQS2 dynamic configuration interface is made of four input ports:

  • config_clock_in—This is the clock signal. All other input signals must be treated as synchronous to this clock. The typical frequency is 25 MHz.
  • config_data—This is the 1-bit serial input through which data is scanned into the calibration blocks. This is common to all configuration blocks, but it will only be scanned into calibrations blocks whose enable input is asserted. For Stratix V GX and Arria V GZ, the configuration data must be input in LSB first ordering. For example, the Stratix V I/O configuration block data must start with padtoinputregisterdelaysetting[0]. For Arria V and Cyclone V devices, the configuration data must be input in MSB first ordering.
  • config_enable—In a generic ALTDQ_DQS2 IP core, the following three config_enable inputs are available:
    • config_io_ena[]—Controls the enable input on the DQ I/Os
    • config_dqs_io_ena[]—Controls the enable input on the DQS I/Os
    • config_dqs_ena[]—Controls the enable input on the DQS logic
    Note: Each of these inputs is wide to control all the scan chain blocks instantiated in the ALTDQ_DQS2 IP core. In a general application, you must assert only one enable input at a time to scan the desired data in the corresponding scan chain block. The enable input must be held high for the entire duration of the scanning process. All other inputs must be held at 0.
    Note: You must deassert the config_enable signal after the last bit of config_data to prevent further data from scanning in. Then, assert the update signal whenever you are ready to copy the scanned in data to the configuration registers.
  • config_update—After scanning all the bits into the desired scan chain blocks, copy them into the configuration register by asserting the config_update signal for one clock cycle.

Section Content
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices
DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices
Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2

Level Two Title