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ALTDQ_DQS2 Features
ALTDQ_DQS2 Device Support
Resource Utilization and Performance
ALTDQ_DQS2 Parameter Settings
ALTDQ_DQS2 Data Paths
ALTDQ_DQS2 Ports
Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example
Arria V Design Example
IP-Generate Command
ALTDQ_DQS2 IP Core User Guide Archives
Document Revision History
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices
DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices
Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
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Instantiating Altera PLL
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.
- Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK.
- On the General tab, specify the parameters as shown in the following figures.
Figure 13. Altera PLL Parameter Settings for Stratix V Devices
- Click Finish.