Visible to Intel only — GUID: sam1412661574535
Ixiasoft
Visible to Intel only — GUID: sam1412661574535
Ixiasoft
ALTDQ_DQS2 Parameter Settings
You can instantiate and parameterize using the IP Catalog and parameter editor GUI, or the ip-generate command through the command-line interface (CLI).
The following table lists the ALTDQ_DQS2 parameter settings.
Parameter Editor GUI Setting |
CLI Parameter | Description | ||
---|---|---|---|---|
Name |
Legal Values | Name |
Legal Values 1 | |
General Settings | ||||
Pin width |
1 to 36 |
PIN_WIDTH | 1 to 36 | This setting specifies the number of data (DQ) pins to make as part of this DQS group. The default value is 9. Cyclone V devices support only x8/x9 DQ/DQS groups. The maximum number of pins including strobes is 12. |
Pin type |
input output bidir |
PIN_TYPE | input output bidir |
This setting specifies the direction of the data pins (input, output, or bidirectional). The default value is bidir (bidir). |
Extra output-only pins |
0 – 36 |
EXTRA_OUTPUT_WIDTH | 0 to 36 | This setting specifies the extra output pins that you need as part of a DQS group. A common use for this setting is to add datamask pins. The default value is 0 (0). |
Memory frequency |
1–1068 |
INPUT_FREQ | 120–1068 | This setting specifies the full-rate clock frequency of the incoming DQS group signal from the external device in MHz. The default value is 300 MHz (300). |
Use DLL Offset Control |
— |
USE_OFFSET_CTRL | true false |
This setting enables dynamic control of the DLL offset. Altera recommends using this setting for test purposes only. For DQS data capture calibration, use the D1, D2, D3, and D4 delay chains. |
Enable hard FIFOs |
— |
USE_HARD_FIFOS | true false |
This setting enables the hard FIFOs (read FIFO for Stratix V devices and read FIFO, latency shifter FIFO and data valid FIFO for Arria V and Cyclone V devices) as part of the ALTDQ_DQS2 IP core. |
Use Capture Clock to clock the read Side of the Hard VFIFO |
— |
USE_DQSIN_FOR_VFIFO_READ | true false |
Turn on this setting when you use the hard data valid FIFO and when the capture clock is not gated. This setting is available only for Arria V and Cyclone V devices. |
Enable dual write clocks |
— |
DUAL_WRITE_CLOCK | true false |
This setting enables the use of separate output clocks for data and strobe. This setting is disabled by default for Arria V and Cyclone V devices. |
Use dynamic configuration scan chains |
— |
USE_DYNAMIC_CONFIG | true false |
This setting enables run‑time configuration of multiple delay chains, phase shifts, and transfer registers. Requires a correctly formatted bitstream. For more information, refer to DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices and DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices. |
Output Path |
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Use half-rate output path |
— |
HALF_RATE_OUTPUT | true false |
This setting doubles the width of the data bus on the FPGA side and clocks the FPGA side interface using the half‑rate clock input. If this setting is enabled, drive the hr_clock_in port with the half‑rate clock signal. When enabling hard read FIFO in a Stratix V device, you must set this parameter to true. This setting is enabled by default. |
Use output phase alignment blocks |
— |
USE_OUTPUT_PHASE_ALIGNMENT | true false |
This setting enables phase shift on the output path based on the delay settings from the DLL. This setting is disabled by default. |
Capture Strobe |
||||
Capture strobe type |
Single Differential Complementary |
CAPTURE_STROBE_TYPE | single differential complementary |
This setting specifies the type of capture strobe (DQS signal from the external device). The default value is Single (single). |
Use inverted capture strobe |
— |
INVERT_CAPTURE_STROBE | true false |
When enabled, this parameter captures data with an inverted capture strobe. Strobe inversion occurs from dqsbusout (an output port from the DQS delay chain block) to the clock input of the DDIO_IN block. This setting is enabled by default. |
DQS phase shift |
0 degrees 45 degrees 90 degrees 135 degrees |
DQS_PHASE_SETTING | 0 1 2 3 |
This setting specifies the phase shift value for the DQS delay chain to shift the incoming strobe in the data valid window during read and write operations. The default value is 90 degrees (2). Arria V and Cyclone V devices support only 0 and 90 degrees. |
Use capture strobe enable block 2 |
— |
USE_DQS_ENABLE | true false |
This setting enables the capture strobe enable block, which allows control over the preamble state of the capture strobe. This setting is disabled by default. This setting is available for Arria V GZ and Stratix V devices only. |
Treat the capture strobe enable as a half-rate signal |
— |
USE_HALF_RATE_DQS_ENABLE | true false |
This setting doubles the width of the capture strobe enable bus on the FPGA side and clocks the FPGA side interface using the half-rate clock input. |
DQS enable phase setting |
0 degrees 45 degrees 90 degrees 135 degrees |
DQS_ENABLE_PHASE_SETTING | 0 1 2 3 |
This setting specifies the value of phase shift to shift the full-rate clock signal that drives the capture strobe enable block. The default value is 0 degrees (0). |
Output Strobe |
||||
Generate output strobe |
— |
USE_OUTPUT_STROBE | true false |
This setting generates an output strobe signal based on the OE signal and the full-rate clock. This setting is enabled by default. |
— |
USE_BIDIR_STROBE | true false |
This setting enables the bidirectional capture strobe (capture strobe and output strobe is on the same port). This setting is disabled by default. |
|
Differential/ complementary output strobe |
— |
DIFFERENTIAL_OUTPUT_STROBE | true false |
This setting enables either the differential or complementary output strobe. This setting is disabled by default. |
Use reset signal to stop output strobe |
— |
USE_OUTPUT_STROBE_RESET | true false |
This setting stops the unidirectional output strobe using a user-provided reset signal. The core_clock_in and the reset_n_core_clock_in signals are required. |
OCT Source |
Output Strobe Enable Data Write Enable Dedicated OCT Enable
|
OCT_SOURCE | 0 1 2 |
This setting specifies the type of input signal to toggle the OCT control:
The availability of the Output Strobe Enable, Data Write Enable,and Dedicated OCT Enable are dependent on PIN_TYPE and USE_BIDIR_STROBE parameters. Default value is Data Write Enable. |
Preamble type |
high low none |
PREAMBLE_TYPE | high low none |
This setting sets the DQS preamble to high (DDR3), low (DDR2), or none:
Note: The ALTDQ_DQS2 IP core does not support DQS tracking.
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