ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

DQS Read Operation

Between 19.227 ms and 19.275 ms when the dqs_readdata_valid signal is held high, data validation is done by comparing data received by the ALTDQ_DQS2 core (read_data_out) against the content in the check_fifo.

ln Stratix V devices, you can choose to enable or disable the hard read FlFO. The read FlFO is in every input data paths. The read FlFO handles full-rate and half-rate conversion only. This example design uses the hard read FlFO. The testbench determines the timing to assert the write enable and read enable ports via the v/i/o_qvld and l/i/o_rden. ln an actual application, you must design your own logic to do so.

The DQS driver begins the DQS read operation when the dqs_read signal is asserted at 19.139 ms, for the entire length of the desired read burst, which in this case is 12 full-rate cycles. The DQS agent also receive the read command, and is ready to send out data. After a specific latency, the agent_output_enable signal is asserted beginning from 19.167 ms to 19.219 ms. During this period, the DQS agent drives clock and data lines of the external memory interface. The oct_enable signal is asserted between 19.155 ms and 19.211 ms. The incoming data (dq) is edge-aligned to the clock (dqs_agent_to_ios).

DQS Read Operation Waveform



Section Content
DQS Delay Chain
Hard Read FIFO

Level Two Title