Visible to Intel only — GUID: sam1412661561607
Ixiasoft
Visible to Intel only — GUID: sam1412661561607
Ixiasoft
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices
The following tables lists the I/O configuration block bit sequence, description, and settings for Arria V GZ and Stratix V devices.
Legend in Figure 7 |
Bit | Bit Name |
Description |
---|---|---|---|
A |
5..0 |
padtoinputregisterdelaysetting |
Connects to the delayctrlin port of the D1 delay chain to control the first I/O buffer‑to-input register delay chain (D1). Sets to tune the DQ delay (read calibration) for DDR applications. For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
B |
11..6 |
padtoinputregisterrisefalldelaysetting |
Connects to the delayctrlin port of the second D1 delay chain to control the second pad‑to‑input register delay chain (D1). For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
C |
17..12 |
outputdelaysetting1 |
Connects to the delayctrlin port of the D5 delay chain to control the output register‑to‑I/O buffer delay chain (D5) in the output path and output enable paths. This delay is for write calibration for DDR application. For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
D |
23..18 |
outputdelaysetting2 |
Connects to the delayctrlin port of the second D5 delay chain to control the output register-to-I/O buffer delay chain (second D5) in the output path and output enable paths. This delay is for write calibration for DDR application. For delay values, refer to the “Programmable IOE Delay” section in the Stratix V Device Datasheet. |
— |
39..24 |
inputclkndelaysetting inputclkdelaysetting dutycycledelaymode dutycycledelaysetting |
Unconfigurable bits. Always set bits to its default value. |
Bit | Bit Name/ Bit |
Default Value (Binary) |
Min. Value |
Max. Value |
Inc. Value |
---|---|---|---|---|---|
5..0 |
padtoinputregisterdelaysetting |
000000 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
11..6 |
padtoinputregisterrisefalldelaysetting |
000000 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
17..12 |
outputdelaysetting1 |
000000 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
23..18 |
outputdelaysetting2 |
000000 |
intrinsic delay |
787.5 ps + intrinsic delay |
12.5 ps |
39..24 |
inputclkndelaysetting inputclkdelaysetting dutycycledelaymode dutycycledelaysetting |
0000000000000000 |
— |
— |
— |