ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

ALTDQ_DQS2 Data Ports

The following table lists the ALTDQ_DQS2 data ports where n= number of DQ pins, m= number of additional output-only DQ pins, x = 0 to (n-1), and y= 0 to (m-1).
ALTDQ_DQS2 Data Ports

Port Name

Type

Width

Description

extra_write_data_in[]

Input

2m = full-rate

4m = half-rate

Receives data signal from the core.

This port connects to the input port of the half-rate data to single-rate data output registers block (Figure 2). In full-rate mode, only the extra_write_data_in[y] and extra_write_data_in[m+y] ports are used.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

extra_write_data_out[]

Output

m

Sends data to the external device.

This port connects to the output port of the output buffer (Figure 2).

This port is supported in Arria V, Cyclone V, and Stratix V devices.

read_data_in[]

Input

n

Receives data from the external device.

This port connects to the input port of the input buffer located between the DQ pin and the DDR input registers block. This is an input-only DQ port that receives data from the external device (Figure 1).

This port is supported in Arria V, Cyclone V, and Stratix V devices.

read_data_out[]

Output

2n = full-rate

4n = half‑rate

Sends the captured data from the external device to the core.

This port connects to the output port of the DDR input register block (Figure 1). The read_data_out[x] port outputs the positive-edge triggered data, and the read_data_out[n+x] port outputs the negative-edge triggered data.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

read_write_data_io[]

Bidirectional

n

Receives and sends data between the core and the external device.

You must assign the bidirectional DQ port with the output termination and input termination assignments.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_data_in[]

Input

2n = full-rate

4n = half-rate

Receives DDR data signal from the core to be sent out to the external device. For example, data to be written to the external memory during write operation.

This port connects to the input port of the half-rate data to single-rate data output registers block (Figure 1). In full-rate mode, the IP core uses only the write_data_in[x] and write_data_in[n+x] ports.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_data_out[]

Output

n

Sends the DDR data signal to the external device. For example, data to be written to the external memory during write operation.

This port connects to the output port of the output buffer located between the DDR output registers block and the DQ‑out pin (Figure 1).

This port is supported in Arria V, Cyclone V, and Stratix V devices.

write_oe_in[]

Input

n = full-rate

2n = half-rate

Receives the gating signal from the core to control the output buffer. For example, gating control when writing data to the external memory during write operation.

This port connects to the input port of the half-rate data to single-rate data output-enable registers block (Figure 1). In full-rate mode, the IP core uses only the write_oe_in[x] port.

This port is supported in Arria V, Cyclone V, and Stratix V devices.

Note: To understand how these ports connect to the IOEs, refer to “I/O Elements” in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook.
The port width applies to full-rate mode, unless otherwise specified.
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