ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

Document Revision History

Table 14.  Document Revision History
Date Version Changes
May 2017 2017.05.08
  • Updated the desciption for DQS enable block in Blocks in DQ and DQS Input Path table.
  • Updated the description for hard data valid FIFO in Capture DDIO to Read FIFO Path section.
  • Updated description for config_data port in ALTDQ_DQS2 Dynamic Configuration Ports table.
  • Updated the description for config_data port in Dynamic Reconfiguration for ALTDQ_DQS2 section.
  • Changed instances of Quartus II to Quartus Prime.
February 2017 2017.02.24 Updated Stratix V and Arria V design examples for Quartus II version 15.1.
May 2016 2016.05.02
  • Updated Cyclone V devices supports only x8/x9 DQ/DQS groups and the maximum number of pins including strobes is 12.
  • Added ALTDQ_DQS2 IP Core User Guide Archives table.
November 2015 2015.11.25
  • Clarified the input ordering for Stratix V GX, Arria V GZ, Arria V GX, Arria V SoC, Cyclone V GX, and Cyclone V SoC devices to config_data port description.
November 2015 2015.11.06
  • Added a note to Pin Width in ALTDQ_DQS2 Parameter Settings table to clarify that Cyclone V devices support maximum pin width of 10.
  • Changed instances of Quartus II to Quartus Prime.
  • Removed topics on generating IP cores and added links to Introduction to Altera IP Cores, Creating Version-Independent IP and Qsys Simulation Scripts, and Project Management Best Practices.
December 2014 2014.12.17 Updated the description for write_strobe_clock_in signal to explain that the signal is a full-rate input clock when you set the IP type to Input for Arria V and Cyclone V devices.
July 2014 2014.07.07

January 2013

2.2

  • Updated note in Figure 3–8 on page 3–10.
  • Added “Additional Information” section.

December 2012

2.1

  • Replaced previous design examples with the following design examples:
  • For Arria V devices: 12.1_AV_BasicDesign.qar
  • For Stratix V devices: 12.1_SV_BasicDesign.qar
  • Made necessary changes in the document to reflect the design examples replacement.

December 2012

2.0

  • Major enhancement to include:
  • Arria V and Cyclone V devices information.
  • Updated “Features” on page 1–1:
  • Included read FIFO, hard FIFO, latency shifter FIFO, and data valid FIFO.
  • “Device Support” on page 1–2
  • Included Arria V and Cyclone V devices.
  • Updated “Parameter Settings” on page 2–1:
  • Updated Table 2–1 on page 2–1 to include new parameters and to update old parameters.
  • Updated “ALTDQ_DQS2 Datapaths” on page 3–1:
  • Updated Figure 3–1 and added notes  (3),  (4), and   (5) to clarify the usage of soft and hard FIFO for different devices and to explain the location of an inversion.
  • Added the following new sections: “DQS Logic” on page 3–2, “Capture DDIO to Read FIFO Path” on page 3–3, and “FIFO Control” on page 3–4.
  • Updated “ALTDQ_DQS2 Ports” on page 3–10:
  • Updated “DQ and DQS Output Path” on page 3–6 to include DQS output path information.
  • Updated Figure 3–5 on page 3–6 and added notes to the figure to help distinguish the device support.
  • Updated Figure 3–6 on page 3–7 to fix the variable typo and to clarify that the figure is for additional pin usage for Stratix V devices.
  • Combined and converted IP cores information to Table 3–3 on page 3–8 for ease of reference.
  • Added Figure 3–7 on page 3–8 to shows the DQ and DQS output path for Arria V and Cyclone V devices.

December 2012

2.0

  • Updated “ALTDQ_DQS2 Ports” on page 3–10:
  • Major update to Figure 3–8 on page 3–10 to clearly define the device family support and the port types.
  • Updated Table 3–3 on page 3–8 to include new ALTDQ_DQS2 data strobe ports and updated old ALTDQ_DQS2 ports.
  • Updated Table 3–5 on page 3–12 to include new ALTDQ_DQS2 data ports and updated old ALTDQ_DQS2 data ports.
  • Updated Table 3–7 on page 3–14 to update the description of the ALTDQ_DQS2 PLL and DLL ports
  • Added Table 3–8 on page 3–14 to introduce the new ALTDQ_DQS2 hard FIFO ports.
  • Updated Table 3–9 on page 3–15 to add new ALTDQ_DQS2 dynamic configuration ports and to update old ports.
  • Added new chapter: “Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction” on page 4–1.
  • Added new chapter: “Instantiating Megafunctions” on page 5–1
  • Added design examples.

September 2010

1.0

Initial release.

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