ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Constraining DQS Strobe Commands set_false_path Commands set_multicycle_path Commands
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

Constraining Outgoing DQS Strobe

The following commands constraint the outgoing DQS strobe. The create_generated_clock command requires the -add option because the strobe_io port is bidirectional. The design sends the data out which centre-aligned to the DQS strobe. The minimum and maximum input delay is assumed to be ±0.25 ns in this reference design. Use the -add option in the set_output_delay command to add the user-defined clock uncertainty values.

Constraining DQS Strobe Commands

create_generated_clock -name dqs_out -source [get_pins{pll_inst/alterapll_inst/altera_pll_i/general[1].gpll�PLL_OUTPUT_COUNTER/divclk}] -phase 0 [get_ports{output_strobe_out}]

set_output_delay -clock { dqs_out } -max 0.150 [get_ports {read_write_data_io[*]}] -add_delay

set_output_delay -clock { dqs_out } -max 0.150 -clock_fall [get_ports {read_write_data_io[*]}] -add_delay

set_output_delay -clock { dqs_out } -min -0.150 [get_ports {read_write_data_io[*]}] -add_delay

set_output_delay -clock { dqs_out } -min -0.150 -clock_fall [get_ports {read_write_data_io[*]}] -add_delay

Figure 26. 


The following set_false_path commands ensure that we are analyzing only the same edge transfers, by removing the opposite edge transfers.

set_false_path Commands

set_false_path -setup -rise_from [get_clocks{pll_inst/alterapll_inst/altera_pll_i/general[2].gpll�PLL_OUTPUT_COUNTER/divclk}] -fall_to [get_clocks{dqs_out}]

set_false_path -setup -fall_from [get_clocks{pll_inst/alterapll_inst/altera_pll_i/general[2].gpll�PLL_OUTPUT_COUNTER/divclk}] -rise_to [get_clocks{dqs_out}]

set_false_path -hold -rise_from [get_clocks{pll_inst/alterapll_inst/altera_pll_i/general[2].gpll�PLL_OUTPUT_COUNTER/divclk}] -rise_to [get_clocks{dqs_out}]

set_false_path -hold -fall_from [get_clocks{pll_inst/alterapll_inst/altera_pll_i/general[2].gpll�PLL_OUTPUT_COUNTER/divclk}] -fall_to [get_clocks{dqs_out}]

The following set_multicycle_path commands ensure that the correct transfer between the DDlO and Read FlFO.

set_multicycle_path Commands

set_multicycle_path -from {*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].capture_reg�HIGH_DFF} -to {*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr�INPUT_DFF_*} -setup -end 0

set_multicycle_path -from {*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].capture_reg�LOW_DFF} -to {*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr�INPUT_DFF_*} -setup -end 0

FIFO control algorithm is necessary. Consider designing some soft FlFOs for this purpose. The following paths can only be set to false path or multicycle if there is calibration algorithm in the system to ensure correct functionalities.

set_false_path Commands

#set_false_path -from {*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr�WRITE_LOAD_DFF_*} -to {*/altdq_dqs2_stratixv:altdq_dqs2_inst/input_path_gen[*].read_fifo_hr�READ_LOAD_DFF_*}

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