F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.3.1. Steps to Run Simulation

The simulation reports "Simulation stopped due to successful completion" if no errors occur.

The same procedure is applicable for PCIe Gen3/4 x16, PCIe Gen3/4 x8x8 and PCIe Gen3/4 x8 design example variants.

Note: When running the simulation with PIPE mode, you must enable the FASTSIM mode.