F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.23 24.1 12.0.0
  • Added Gen3 and Gen4 terms in the Terms and Definitions table in the Acronyms section.
  • Updated supported simulators and development kit in the F-Tile Avalon-ST IP Design Examples table in the Design Example Description section.
  • Updated the PIO Application naming to PIO Design Example for PCI Express G4 in all figures and sections using the name.
  • Updated the SR-IOV Applications naming to F-Tile Avalon-ST SR-IOV Example Design in all figures and sections using the name.
  • Updated Performance Design Example section with the supported frequency of only 500 MHz.
  • Updated Generating the Design Example section with PIPE mode simulation settings.
  • Removed note for the multiple driver issue for VCS* and Xcelium* simulators and added note for PIPE mode simulation in the Steps to Run Simulation section.
  • Added information about how to run FASTSIM + PIPE mode simulation in Steps to Run Simulation : VCS* section.
  • Added information about how to run FASTSIM + PIPE mode simulation in Steps to Run Simulation : VCS* MX section.
  • Added information about how to run FASTSIM + PIPE mode simulation in Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition section.
  • Added information about how to run FASTSIM + PIPE mode simulation in Steps to Run Simulation : Xcelium* section.
  • Added information about how to run FASTSIM + PIPE mode simulation in Steps to Run Simulation : Riviera-PRO* section.
  • Updated Compiling the Design Example section with a note about PIPE mode simulation setting.
  • Updated Hardware and Software Requirements section with Linux software support and design example testing.
2024.01.29 23.4 11.0.0
  • PIO Design Example Testbench: Simulation waveform updated
  • Compiling the Design Example: Information updated
2023.11.03 23.3 10.0.0
  • Steps to Run Simulation: Note added about fix to address simulation errors for VCS and Xcelium
  • Programmed Input/Output Design Example Limitation: New section added
  • SR-IOV Design Example Limitation: New section added
  • Steps to Run Simulation: New section added
2023.04.27 23.1 8.1.0
  • Updated product family name to "Intel Agilex 7."
  • Design Example Description: Hardware column updated in F-Tile Avalon-ST IP Design Examples table
  • Design Example Description: Note added about 10-bit tag completer feature & simulator support in FASTSIM.
  • Generating the Design Example: Step 11(c) development kit information updated
  • Generating the Design Example: Example Designs Tab screenshot updated
  • Simulating the Design Example: Steps to run simulation table removed
  • Steps to Run Simulation: New section added with sub-sections for individual simulators
2023.02.03 22.4 8.0.0 Added requirements for the reference clock for the System PLL to the F-Tile Reference and System PLL Clocks IP section.
2022.10.04 22.3 7.0.0
Sections Updated:
  • Design Example Description: New column Hardware added in table F-Tile Avalon-ST IP Design Examples
  • Generating the Design Example: Step 11(c) updated
  • Simulating the Design Example: Command updated for FASTSIM mode for VCS simulator in Steps to Run Simulation table
  • Hardware and Software Requirements: All contents updated
  • Running the SR-IOV Design Example: Steps (5) and (6) updated
  • Running the Performance Design Example: Note added about 500 MHz hardware test support
  • Running the Performance Design Example: Step (7) added
  • Running the Performance Design Example: Figures illustrating Write, Read, Simultaneous Write and Read operations added
  • Running the Performance Design Example: Test Results updated for Write, Read, Simultaneous Write and Read operations
  • Running the Performance Design Example: Performance Design Example Data Throughput information added
2022.07.14 22.2 6.0.0
  • Design Example Description: F-Tile Avalon-ST IP Design Examples table updated
  • Performance Design Example: New design example information added
  • Generating Design Example: Step 11c added & Example Designs Tab GUI screenshot updated
  • Simulating the Design Example: Commands updated for all simulators in Steps to Run Simulation table
  • Performance Design Example Testbench: New section added
  • Hardware and Software Requirements: New section added
  • Installing the Linux Kernel Driver: Introductory description modified
  • Running the Design Example: Test Operations Supported by the F-Tile Avalon-ST IP for PCI Express Design Examples table reorganized and updated
  • Running the PIO Design Example: GUI screenshots for sample transcripts for automatic and manual modes updated
  • Running the SR-IOV Design Example: Link Test Menu GUI screenshot updated
  • Running the Performance Design Example: New section added
2021.12.17 21.4 4.0.0
  • SR-IOV Design Example related information added to Design Example Description chapter
  • SR-IOV Design Example related information added to Quick Start Guide chapter
  • Generating tile files information added to Quick Start Guide chapter
  • Xcelium simulator information added to Steps to run simulation table
  • Running the SR-IOV Design Example section added to Quick Start Guide chapter
2021.10.04 21.3 3.0.0
  • Updated Configurations Supported by the F-Tile Avalon-ST Design Examples Table
  • Added PCIe Gen3/Gen4 x8 Design Example Variant block diagram
  • Added PIO Design Example for PCI Express G4 (APPS) component information in Functional Description
  • Added Block Diagram for the PCIe x8 PIO Design Example Simulation Testbench block diagram
  • Added Platform Designer System Contents for F-Tile Avalon®-ST IP for PCI Express PIO Design Example Gen4 x8 variant screenshot
  • Update figure Directory Structure for the Generated Design Example
  • Procedure updated in Simulating the Design Example
  • Added VCSMX simulator information to Steps to Run Simulation table.
2021.07.31 21.2 2.0.0 Initial Release