F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.2.2. SR-IOV Design Example Limitation

F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example fails to write back-to-back transactions correctly.

For the SR-IOV design example, there is no support for the back-to-back TLP packets from the host processor.

The design is intended to handle simple read-write instructions based on the TLP command. TLP transaction of memory write request (MWr) and write the data to the designated RAM memory space. As for the TLP transaction of memory read request (MRd), the design will read the data from RAM memory space and return completion with data (CplD).

No upstream request from the F-Tile Avalon-ST SR-IOV Example Design. The data and address requested to access the F-Tile Avalon-ST SR-IOV Example Design must be DW-aligned. The maximum data transfer is 128 bits.