F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition

Working Directory

<example_design>/ pcie_ed_tb/pcie_ed_tb/sim/mentor/

Instructions

  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
  3. set TOP_LEVEL_NAME "pcie_ed_tb.pcie_ed_tb" [required for Windows environment only]
  4. Enable FASTSIM mode or FASTSIM + PIPE mode for simulation. You can skip this step if none of these modes is required for your simulation.
    For FASTSIM + PIPE mode:
    Note: Enable PIPE Mode Simulation box must be checked during generation of design example. PIPE mode is not supported for ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition.
    set USER_DEFINED_COMPILE_OPTIONS “+define+gdrb_GDR_PCIE_SS_DV\ +define+IP7581SERDES_UX_SIMSPEED”
    For FASTSIM mode:
    set USER_DEFINED_COMPILE_OPTIONS “+define+IP7581SERDES_UX_SIMSPEED”
    
  5. ld_debug
  6. run -all
  7. A successful simulation ends with the following message:
    "Simulation stopped due to successful completion!"