F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2. Design Example Description

The F-Tile Avalon-ST IP for PCI Express Design Example is a simple design to demonstrate the establishment of PCIe connectivity of F-Tile FPGA in Quartus® Prime. The design performs write and read sequences from the host processor to the target device through PCIe Quartus® Prime Hard IP. The Programmed Input/Output (PIO) application block is needed to handle the translation from PCIe TLP to AVMM protocol.

Table 2.  F-Tile Avalon-ST IP Design Examples
Design Example Hard IP Mode Simulation Hardware
PIO Gen4 x16 512-bit Endpoint

Supports VCS* , VCS* MX, QuestaSim* , Xcelium* and Riviera-PRO* simulators.

Agilex™ 7 F-Series F-Tile FPGA Development Kit DK-DEV-AGF027F1ES (F-Tile B0 OPN: AGFB027R24C2E2VR2)

Gen4 x8x8 256-bit Endpoint
Gen4 x8 256-bit Endpoint
Gen3 x16 512-bit Endpoint
Gen3 x8x8 256-bit Endpoint
Gen3 x8x8 256-bit Endpoint
SR-IOV Gen4 x16 512-bit Endpoint
Gen3 x16 512-bit Endpoint
Performance Gen4 x16 512-bit Endpoint

Supports VCS* simulators.

Note: Design examples only support the default settings in the Parameter Editor of the F-Tile Avalon Streaming IP for PCI Express.
Note: Design examples do not support 10-bit tag completer feature. Running the design example on host machine enforce 10-bit tag at PCIe Gen4, can cause completion timeout or system crashed.