F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)

This is the F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) with the parameters you specified in the IP parameter editor. This component drives TLP data received to the PIO Design Example for PCI Express G4. The DUT component is the F-Tile Avalon-ST IP for PCI Express Hard IP configured as Endpoint interacting with the root complex/switch at the other end. The DUT component translates the PCIe serial link transfer interface to Avalon-ST interface.