F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.4. Compiling the Design Example

  1. Navigate to <project_dir>/pcie_avst_f_0_example_design/ and Click on pcie_ed.qpf to open example design project.
  2. On the Processing menu, select Start Compilation.
    Note: If the Enable PIPE Mode Simulation box is checked when you generate the design example, you must uncheck the box and regenerate the design example as the PIPE mode is not supported for hardware compilation.
  3. Examine the design compilation result like resource utilization and timing result.
  4. Close your example design project.
    Note: You cannot change the PCIe pin allocations in the Quartus® Prime project. However, to ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by this IP.