Visible to Intel only — GUID: gzm1615420289247
Ixiasoft
Visible to Intel only — GUID: gzm1615420289247
Ixiasoft
2.1. Programmed Input/Output Design Example
The PCIe F-Tile Design Example is designed to highlight the application of PCIe Gen4 in F-Tile. The PCIe IP run up to 500 MHz at user interface with the maximum data width of 512 bits for Gen4 x16 and 256 bits for each of the two Gen4 x8 ports.
The clock frequency supplied from the coreclkout_hip is limited to 500 MHz.
- F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)
- Programmable I/O (PIO) Design Example for PCI Express G4
- On-Chip Memory (MEM)
The PIO design example performs memory transfers from a host processor to a target device. In this example, the host processor requests single-dword MemRd and MemWr TLPs.
The PIO design example automatically creates the required files to simulate and compile in the Quartus® Prime software. The design example covers a wide range of parameters. However, it does not cover all possible parameterizations of the F-Tile Hard IP for PCIe.