F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.1.1.2.3. Avalon-MM Interface

When Avalon-MM command from the Read Write Module is available, Avalon-MM Master State Machine checks the Completion Buffer watermark to ensure it is not full and the Avalon-MM Master, the driver to the On-Chip memory is not in waitrequest. When the conditions are met, the Avalon-MM Master State Machine gets Avalon-MM command or data and issues the write/read to the Avalon-MM Master. Concurrently the Avalon-MM data is directly flushed to the Avalon-MM Master. For read sequence, the returned data from the Avalon-MM Master is stored at Completion Buffer and ready to move to Completion module.