F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.3.1.5. Steps to Run Simulation : Riviera-PRO*

Simulation Flow starting with Quartus® Prime 22.4 version

  1. Generate the example design
  2. Run the simulation commands below
    1. cd <my_design>/pcie_ed_tb/pcie_ed_tb/sim/aldec
    2. Invoke vsim by using command:
      vsim -c -do rivierapro_setup.tcl
    3. Note: Enable FASTSIM mode or FASTSIM + PIPE mode for simulation. You can skip this step if none of these modes is required for your simulation.
      For FASTSIM + PIPE mode:
      Note: Enable PIPE Mode Simulation box must be checked during generation of design example.
      set USER_DEFINED_COMPILE_OPTIONS “+define+gdrb_GDR_PCIE_SS_DV\ +define+IP7581SERDES_UX_SIMSPEED”
      For FASTSIM mode only:
      set USER_DEFINED_COMPILE_OPTIONS “+define+IP7581SERDES_UX_SIMSPEED”
      
    4. set USER_DEFINED_ELAB_OPTIONS "-nocvg -dbg -05"
    5. ld
    6. run -all
    7. A successful simulation ends with the following message:
      "Simulation stopped due to successful completion!"