F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

3.3.2. Testbench

The testbench uses a test driver module, altpcietb_bfm_rp_gen4_x16.sv, to initiate the configuration and memory transactions. At startup, the test driver module displays information from the Root Port and Endpoint Configuration Space registers, so that you can correlate to the parameters you specified using the Parameter Editor.

The example design and testbench are dynamically generated based on the configuration that you choose for the F-Tile IP for PCIe. The testbench uses the parameters that you specify in the Parameter Editor in Quartus® Prime.

This testbench simulates up to a x16 PCI Express link using the serial PCI Express interface. The testbench design does allow more than one PCI Express link to be simulated at a time. The following figure presents a high level view of the PIO design example.

Figure 21. PIO Design Example Simulation Testbench
The top-level of the testbench instantiates the following main modules:
  • altpcietb_bfm_rp_gen4x16.sv —This is the Root Port PCIe* BFM. 
    //Directory path
<project_dir>/pcie_avst_f_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_<ver>/sim
  • pcie_ed_dut.ip: This is the Endpoint design with the parameters that you specify.
    //Directory path
<project_dir>/pcie_avst_f_0_example_design/ip/pcie_ed
  • pcie_ed_pio0.ip: This module is a target and initiator of transactions for the PIO design example.
    //Directory path
<project_dir>/pcie_avst_f_0_example_design/ip/pcie_ed
  • pcie_ed_sriov0.ip: This module is a target and initiator of transactions for the SR-IOV design example. 
    //Directory path 
<project_dir>/pcie_avst_f_0_example_design/ip/pcie_ed

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.

For more details on the Root Port BFM, refer to the TestBench chapter of the Intel FPGA F-Tile Avalon® Streaming IP for PCI Express User Guide.


Section Content
Test Driver Module
PIO Design Example Testbench
SR-IOV Design Example Testbench
Performance Design Example Testbench

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