F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.3.2. Performance Design Example Simulation Testbench

The simulation testbench instantiates the performance design example and a Root Port BFM to interface with the target Endpoint.

Figure 15. Performance Design Example Simulation Testbench

The Performance design example simulation testbench is similar to the PIO design example simulation testbench. It issues Memory Write cycles to set up and trigger the Performance design example to issue 10 Memory Writes followed by 10 Memory Reads for functional check. No throughput figure is generated from the simulation.