F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.3.1.2. Steps to Run Simulation : VCS* MX

Working Directory

<example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcsmx/

Instructions

  1. Run the following commands:
    For FASTSIM + PIPE mode:
    Note: Enable PIPE Mode Simulation box must be checked during generation of design example.
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+gdrb_GDR_PCIE_SS_DV\ +define+RTLSIM\ +define+SSM_SEQUENCE\ -sverilog\ +define+IP7581SERDES_UX_SIMSPEED\ " USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ -debug_access+all\ " USER_DEFINED_SIM_OPTIONS="" | tee simulation_log
    For FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sverilog\ +define+QUARTUS_ENABLE_DPI_FORCE\ " USER_DEFINED_ELAB_OPTIONS="\$QUARTUS_INSTALL_DIR/eda/sim_lib/quartus_dpi.c\ -debug_access+f\ +vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    For non-FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sverilog\ +define+QUARTUS_ENABLE_DPI_FORCE\ " USER_DEFINED_ELAB_OPTIONS="\$QUARTUS_INSTALL_DIR/eda/sim_lib/quartus_dpi.c\ -debug_access+f\ +vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The commands above are single-line commands.
  2. A successful simulation ends with the following message,
    "Simulation stopped due to successful completion!"
    in the simulation.log file that was generated.
Note: To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in noninteractive mode, delete the simv and simv.daidir)
  1. Open the vcsmx_setup.sh file and add a debug option to the VCS command:
    vcs -debug_access+all
  2. Compile the design example:

    For FASTSIM + PIPE mode:
    Note: Enable PIPE Mode Simulation box must be checked during generation of design example.
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+gdrb_GDR_PCIE_SS_DV\ +define+RTLSIM\ +define +IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sverilog\ "USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\" USER_DEFINED_SIM_OPTIONS="" SKIP_SIM=1
    For FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+IP7581SERDES_UX_SIMSPEED\ +define+SSM_SEQUENCE\ -sverilog\ " USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" SKIP_SIM=1
    For non-FASTSIM mode:
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sverilog\ " USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" SKIP_SIM=1
    Note: The commands above are single-line commands.
  3. Start the simulation in interactive mode:
    simv -gui &