F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.2.1.2.3. Completion

The Completion submodule stores the necessary header information from the incoming MRd instruction and repackages the acquired information into a CplD header. The CplD header is released together with the fetched data from targeted Segram.