F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.1.1.5. Reset Release IP

This IP holds a control circuit in reset until the device has fully entered user mode. The FPGA asserts the INIT_DONE output to signal that the device is in user mode. The Reset Release IP generates an inverted version of the internal INIT_DONE signal to create the nINIT_DONE output that you can use for your design.The nINIT_DONE signal is high until the entire device enters user mode. After nINIT_DONE asserts (low), all logic is in user mode and operates normally. You can use the nINIT_DONE signal in one of the following ways:
  • To gate an external or internal reset.
  • To gate the reset input to I/O PLLs.
  • To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers.
  • To synchronously drive register reset input ports in your design.
Note: For more information on Reset Release IP, refer to Agilex™ 7 Configuration User Guide.
Note: For more information about the F-Tile Reference and System PLL Clocks IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide