F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.1.1.2.5. Width Adapter

Width Adapter converts the Avalon-ST signals from 256 bit @ 500 MHz to 512 bit @ 250 MHz. This adaptation is to maintain data bandwidth to reuse the existing BAM architecture and to interface between the two clock domains. Features like TX and RX Credit Interface, Error Interface, FLR Interface, CII Interface and Interrupt Interface are not used in the design example. This is applicable for PCIe 1x8 and 2x8 design example variants only.