F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.3. Simulating the Design Example

Generating tile files

The tile files are generated during the design example generation. Running Support-Logic Generation manually is not required before simulating the design example.

Tile files generation is a required step before simulation if you created your design with the F-Tile Avalon-ST IP for PCI Express from scratch. You can run Analysis & Elaboration on the Processing menu in the Quartus® Prime Pro Edition software to generate the F-Tile specific tiles file for your design. The Support-Logic Generation command runs automatically as part of the process.

A successful tile file generation results in the <IP_instance_name>__tiles.x files where x represents the necessary file extensions. The generated files are located in your project directory and contain the full netlist for simulation and synthesis.

Figure 20. Procedure
  1. Run the simulation script under <example_design>/pcie_ed_tb/pcie_ed_tb/sim/<simulator> directory for the simulator of your choice. Refer to the table below.
  2. Analyze the results.
Note: F-Tile does not support parallel PIPE simulations.