F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

2.2.1.2.1. Access Parser

Access Parser is a submodule to decode and validate the incoming instruction whether it is valid and good to proceed to the next phase of processing. It ensures the target address and data is double word aligned. If the received MWr instruction is not fulfilling the requirement, it is silently dropped. While for MRd instruction which does not fulfill the requirement, it completely aborts.