F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 683372
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.1.1.4. F-Tile Reference and System PLL Clocks IP

This IP is required for F-Tile PCIe interface implementation to configure the reference clock for the FGT PMA and System PLL. The clock from this IP is a logical connection. It is physically inside the F-Tile Avalon Streaming Intel FPGA IP for PCI Express Hard IP. The main clock of the PIO design example originates from coreclkout_hip of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express Hard IP running at 500 MHz. The clock originates from the System PLL.

The reference clock to the System PLL must adhere to the following requirements:
  • If compliance to PCIE link training timing specifications is required, the reference clock to the System PLL must be available and stable before device configuration begins. You must set the Refclk is available at power-on parameter in the System PLL IP to On. You must derive the reference clock from an independent and free-running clock source. Alternately, if the reference clock from the PCIe link is guaranteed available before device configuration begins, you can use it to drive the System PLL. Once the PCIe link refclk is alive, it can never be allowed to go down.
  • If compliance to PCIE link training timing specifications is not required and the reference clock to the System PLL may not be available before device configuration begins, you must set the Refclk is available at power-on parameter in the System PLL IP to Off. In this case, you may use the reference clock from the PCIE link to drive the System PLL. The System PLL does not lock to the reference until you perform the Global Avalon memory-mapped interface write operations signaling that the reference clock is available.
    Note: Refer to the Example Flow to Indicate All System PLL Reference Clocks are Ready section in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide to trigger the System PLL to lock to the reference clock.

Once the reference clock for the System PLL is up, it must be stable and present throughout the device operation and must not go down. If you are not able to adhere to this requirement, you must reconfigure the device.

Level Two Title