F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.7. Running the Design Example

Table 3.  Test Operations Supported by the F-Tile Avalon-ST IP for PCI Express Design Examples
Operations Required BAR

Supported by F-Tile Avalon Streaming IP for PCIe Design Examples

PIO SR-IOV Performance

0: Link test - 100 writes and reads

0 Yes Yes No

1: Write memory space

0 Yes Yes No

2: Read memory space

0 Yes Yes No

3: Write configuration space

N/A No No No

4: Read configuration space

N/A No No No

5: Change BAR for PIO

N/A Yes Yes No

6: Change device

N/A Yes Yes No

7: Enable SR-IOV

N/A No Yes No

8: Do a link test for every enabled virtual function belonging to the current device

N/A No Yes No

9: Perform DMA for Throughput

0 No No Yes

10: Quit program

N/A Yes Yes Yes