F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3. Quick Start Guide

Using Quartus® Prime software, you can generate a Programmed I/O (PIO) design example or a Single Root Input/Output Virtualization (SR-IOV) design example for the Intel® FPGA F-Tile Avalon® -ST Hard IP for PCI Express* IP core. The generated design example reflects the parameters that you specify. The PIO example transfers data from a host processor to a target device. This design example automatically creates the files necessary to simulate and compile in the Quartus® Prime software. You can download the compiled design to your FPGA Development Board. To download to custom hardware, update the Quartus® Prime Settings File (.qsf) with the correct pin assignments .

Figure 16. Development Steps for the Design Example