F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 5/23/2024
Public
Document Table of Contents

3.7.2. Running the SR-IOV Design Example

Here are the steps to test the SR-IOV design example on hardware:
  1. Run the Intel FPGA IP PCIe link test by running the sudo ./intel_fpga_pcie_link_test command and then select the option 1: Manually select a device.
  2. Enter the BDF of the physical function for which the virtual functions are allocated.
  3. Enter BAR “0” to proceed to the test menu.
  4. Enter option 7 to enable SR-IOV for the current device.
  5. Enter the number of virtual functions to be enabled for the current device.
    Figure 28. Link Test Menu
    Note: To disable VF for the current device, repeat Step 4: Select option 7 to enable SR-IOV, enter 0 for the number of VFs to be enabled.
    Note: Type 'lspci -d 1172:' in a new terminal to determine the BDFs of the newly enabled VFs.
  6. In a new terminal, run the
    lspci –d 1172: | grep -c “Altera”
    command to verify the enumeration of PFs and VFs. The expected result is the sum of the number of physical functions and number of virtual functions. In this example, there are 2 PFs and 32 VFs are enabled for each PF. Running this command returns 66 as shown in the figure below.
    Figure 29. lspci command
  7. Enter option 8 to perform a link test for every enabled virtual function allocated for the physical function. The link test application performs 100 memory writes with a single dword of data each and then reads the data back for checking. The application prints the number of virtual functions that failed the link test at the end of the testing.
    Figure 30. Test Result