F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Design Example for PCI Express G4 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Design Example for PCI Express G4 x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design
2.2.1.2. F-Tile Avalon-ST SR-IOV Example Design x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example Performance Design Example Data Throughput
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

3.7.3. Running the Performance Design Example

Note: The Performance Design Example hardware test is currently supported at 500 MHz only.
  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application: 
    $ make
  3. Run the test: 
    $ sudo ./intel_fpga_pcie_link_test
    You can run the Intel FPGA IP PCIe link test application in manual or automatic mode. Select from:
    • In automatic mode, the application automatically selects the device. The test selects the Intel PCIe device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
    • In manual mode, the test queries you for the bus, device, and function number and BAR.
    For the Agilex™ 7 Development Kit, you can determine the BDF by typing the following command: 
    $ lspci -d 1172:
  4. Here are sample transcripts for automatic and manual modes:
    Figure 31. Automatic Mode
    Figure 32. Manual Mode
  5. To perform DMA for throughput test, enter option “9” and press Enter key to proceed.
  6. Enter number of DMA iterations to be carried out and then press Enter key to select the type of DMA operation, “0” for write operation (device to host), “1” for read operation (host to device) and “2” for simultaneous write and read operations.
  7. Select payload size for the TLPs used for the throughput test.

Here are block diagrams and sample test results for write only, read only and simultaneous write and read for 10 iterations respectively.

Figure 33. Write Only Operation
Figure 34. Write Only Test Result
Figure 35. Read Only Operation
Figure 36. Read Only Test Result
Figure 37. Simultaneous Write and Read Operation
Figure 38. Simultaneous Write and Read Test Result

Performance Design Example Data Throughput

The following test result is obtained using the hardware and software as mentioned in Hardware and Software Requirements.

The data throughput values may vary especially when a different host system is used.

Table 4.  Data Throughput
TLP Payload Size (Byte) Data Throughput
Memory Write (GB/s) Memory Read (GB/s) Simultaneous Write and Read
Write (GB/s) Read (GB/s)
64 22.80 21.08 17.86 17.63
128 26.40 25.67 22.72 22.38
256 28.69 27.85 26.31 25.88
512 29.97 29.12 28.02 28.54
Note: Data throughput at 16 and 32 bytes TLP payload size does not meet expected throughput values. It may be addressed in the future Quartus® Prime software release.
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