Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

5. Clocking and Reset Requirements

The transmit clock (clk_txmac/clk_tx_xmii) is derived from TX IOPLL of the UX PMA Hard IP. The reference frequency is the output from the UX tx_clkout [0]. The PLL converts the frequency from 161.13 MHz to 312.5 MHz. This clock is guaranteed stable when tx_ready is high.

The receive clock (clk_rxmac/clk_rx_mii) is derived from RX CDR of the SM UX PMA Hard IP. The reference frequency is the output from the UX rx_clkout [0]. The PLL converts the frequency from 161.13 MHz to 312.5 MHz. This clock is guaranteed stable when rx_is_lockedtodata is high.

The transceiver calibration clock must be between 100 MHz and 125 MHz as set by the PMA blocks.

The Avalon® memory-mapped clock (clk_status) is nominally 100 MHz but can be as high as 125 MHz.

Figure 12. Clocks