Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

5.1. Reset Requirements

With respect to IP reset requirements, only the PMA digital reset is considered. The reset controller has soft reset signals that are asserted by the CSR and three asynchronous resets that are asserted externally.
Reset Connection

Reset Sequence or Initialization

The reset sequencing is handled by the core’s reset controller. Asserting a reset on the csr_rst_n signal triggers the reset sequence. When the csr_rst_n reset is asserted, the rx_pcs_ready and tx_lanes_stable signals go low and can only go back high after deasserting the reset.

The CSR register read/write must wait at least 2 clock cycles after the csr_rst_n release or assertion. Altera recommends waiting for 10 clock cycles. You can also reset the TX and RX datapaths independently by toggling tx_rst_n and rx_rst_n respectively.

Figure 13. Reset Sequence