Visible to Intel only — GUID: vfx1707464346289
Ixiasoft
Visible to Intel only — GUID: vfx1707464346289
Ixiasoft
5.1. Reset Requirements
Reset Sequence or Initialization
The reset sequencing is handled by the core’s reset controller. Asserting a reset on the csr_rst_n signal triggers the reset sequence. When the csr_rst_n reset is asserted, the rx_pcs_ready and tx_lanes_stable signals go low and can only go back high after deasserting the reset.
The CSR register read/write must wait at least 2 clock cycles after the csr_rst_n release or assertion. Altera recommends waiting for 10 clock cycles. You can also reset the TX and RX datapaths independently by toggling tx_rst_n and rx_rst_n respectively.