Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813652
Date 7/22/2024
Public
Document Table of Contents

2. Low Latency 40G Ethernet Intel® FPGA IP Parameters

The Low Latency 40G Ethernet Intel® FPGA IP parameter editor for Agilex™ 5 devices has an IP tab with two sub-tabs, the Main tab and the Example Design tab.

For information about the Example Design tab, refer to the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs .

Table 7.   Low Latency 40G Ethernet Intel® FPGA IP Parameters: Main Tab
Parameter Range Default Setting Description
General
Device family Agilex 5 Supports Agilex™ 5 devices.
Protocol speed 40GbE 40GbE Selects the Ethernet data rate.
Ready latency 0, 3 0 Selects the Ready Latency value on the TX client interface. Ready Latency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP asserts the l2_tx_ready signal to the clock cycle in which the IP can accept data on the TX client interface. Refer to the Avalon® Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the TX datapath.

PCS/PMA Options
Enable SyncE Enabled, Disabled Disabled Exposes the RX recovered clock as an output signal. This feature supports the Synchronous Ethernet standard described in the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) G.8261, G.8262, and G.8264 recommendations.
Enable cdr dedicated clk Enabled, Disabled Disabled When enabled, the recovered clock is routed through the clk_ref pins which uses the clk_ref pin. This option is available only when you enable Enable SyncE .
PHY reference frequency 156.25 MHz, 312.5 MHz, 322.265625 MHz 156.25 MHz Sets the expected incoming PHY clk_ref_p reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100 ppm).
MAC Options
Enable TX CRC insertion Enabled, Disabled Enabled When enabled, TX MAC computes and inserts the CRC-32 checksum in the out-going Ethernet frame. When disabled, the TX MAC does not compute a 32-bit FCS in the TX MAC frame. Instead, the client must provide frames with at least 64 bytes, plus the Frame Check Sequence (FCS).
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Ethernet Standard. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable MAC stats counters Enabled, Disabled Enabled When enabled, the IP includes statistics counters that characterize TX and RX traffic. The statistics module also supports shadow requests that verify counts by taking snapshots of intermediate results.
Enable Strict SFD check Enabled, Disabled Disabled When enabled, the IP can implement strict SFD checking, depending on register settings.
Flow Control Options
Enable MAC flow control Enabled, Disabled Disabled When enabled, the IP implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames.
Number of queues in priority flow control 1-8 1 Specifies the number of queues used in managing flow control.
Configuration, Debug and Extension Options
Enable JTAG to Avalon Master Bridge Enabled, Disabled Disabled

If turned on, the IP includes a JTAG to Avalon® memory-mapped interface master bridge connecting internally to status and reconfiguration registers.

This allows you to run the Ethernet Tool Kit using the System Console.

Analog Parameters

For more information, refer to GTS Transceiver PHY User Guide.

Figure 2. Analog Parameters tab