Visible to Intel only — GUID: mwh1411073374783
Ixiasoft
Visible to Intel only — GUID: mwh1411073374783
Ixiasoft
3.7.9. Verifying Hardware in System Console
You can use the Intel® Quartus® Prime System Console to verify your system design. The design example files include scripts that exercise your system using System Console Tcl commands. The example uses a JTAG-to-Avalon Master Bridge component to drive the slave components, instead of a Nios® II processor system.
The \quartus_ii_projects_for_boards\<development_board>\system_console directory contains the run_sweep.tcl, base_address.tcl, and test_cases.tcl scripts. You use these scripts to set up and run memory tests on the development board projects. You can view the scripts to help you understand the System Console commands that drive the slave component registers. The scripts work with any board, if you keep the same Platform Designer system structure.
The run_sweep.tcl file is the main script, which calls the other two scripts. The base_address.tcl file includes information about the base addresses of the slave components from the previous chapters. If you change the base addresses of the slave components, you must also change the addresses in the base_address.tcl file. The test_cases.tcl file includes settings for memory span, memory block sizes, and memory block trail distance.
The run_sweep.tcl file contains Tcl commands for the following actions:
- Initialize the components
- Adjust test parameters
- Start the PRBS pattern checker, PRBS pattern generator, and RAM controller
- Continuously poll the stop and fail bits in the PRBS checker
Section Content
Open the Tutorial Project
Add the JTAG-to- Avalon Master Bridge
Debug with System Console