Visible to Intel only — GUID: hco1416491416491
Ixiasoft
Visible to Intel only — GUID: hco1416491416491
Ixiasoft
7.2.3. Parameterizing Memory Controllers
Parameterizing Memory Controllers with UniPHY IP
The Parameter Settings page in the parameter editor allows you to parameterize the following settings for the LPDDR2, DDR2, DDR3 SDRAM, QDR II, QDR II+ SRAM, RLDRAM II, and RLDRAM 3 memory controllers with the UniPHY IP:
- PHY Settings
- Memory Parameters
- Memory Timing
- Board Settings
- Controller Settings
- Diagnostics
The messages window at the bottom of the parameter editor displays information about the memory interface, warnings, and errors if you are trying to create something that is not supported.
Enabling the Hard Memory Interface
For Arria V and Cyclone V devices, enable the hard memory interface by turning on Interface Type > Enable Hard Memory Interface in the parameter editor. The hard memory interface uses the hard memory controller and hard memory PHY blocks in the Arria V and Cyclone V devices.
The half-rate bridge option is available only as an SOPC Builder component, Avalon-MM DDR Memory Half-Rate Bridge, for use in a Platform Designer project.
Section Content
PHY Settings for UniPHY IP
Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP
Memory Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP
Memory Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP
Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP
Memory Timing Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP
Memory Timing Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP
Memory Parameters for RLDRAM 3 UniPHY Intel FPGA IP