Visible to Intel only — GUID: hco1416491411379
Ixiasoft
Visible to Intel only — GUID: hco1416491411379
Ixiasoft
7.2.1.5. RLDRAM II Controller with UniPHY Intel FPGA IP Interfaces
Interface Name |
Interface Type |
Description |
---|---|---|
pll_ref_clk interface |
||
pll_ref_clk |
Clock input. |
PLL reference clock input. |
global_reset interface |
||
global_reset_n |
Reset input |
Asynchronous global reset for PLL and all logic in PHY. |
soft_reset interface |
||
soft_reset_n |
Reset input |
Asynchronous reset input. Resets the PHY, but not the PLL that the PHY uses. |
afi_reset interface |
||
afi_reset_n |
Reset output (PLL master/no sharing) |
When the interface is in PLL master or no sharing modes, this interface is an asynchronous reset output of the AFI interface. This interface is asserted when the PLL loses lock or the PHY is reset. |
afi_reset_export interface |
||
afi_reset_export_n |
Reset output (PLL master/no sharing) |
This interface is a copy of the afi_reset interface. It is intended to be connected to PLL sharing slaves. |
afi_reset_in interface |
||
afi_reset_n |
Reset input (PLL slave) |
When the interface is in PLL slave mode, this interface is a reset input that you must connect to the afi_reset_export_n output of an identically configured memory interface in PLL master mode. |
afi_clk interface |
||
afi_clk |
Clock output (PLL master/no sharing) |
This AFI interface clock can be full‑rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL master or no sharing modes, this interface is a clock output. |
afi_clk_in interface |
||
afi_clk |
Clock input (PLL slave) |
This AFI interface clock can be full‑rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL slave mode, you must connect this afi_clk input to the afi_clk output of an identically configured memory interface in PLL master mode. |
afi_half_clk interface |
||
afi_half_clk |
Clock output (PLL master/no sharing) |
The AFI half clock that is half the frequency of the afi_clk.When the interface is in PLL master or no sharing modes, this interface is a clock output. |
afi_half_clk_in interface |
||
afi_half_clk |
Clock input (PLL slave) |
The AFI half clock that is half the frequency of the afi_clk.When the interface is in PLL slave mode, you must connect this afi_half_clk input to the afi_half_clk output of an identically configured memory interface in PLL master mode. |
memory interface |
||
mem_a |
Conduit |
Interface signals between the PHY and the memory device. |
mem_ba |
||
mem_ck |
||
mem_ck_n |
||
mem_cs_n |
||
mem_dk |
||
mem_dk_n |
||
mem_dm |
||
mem_dq |
||
mem_qk |
||
mem_qk_n |
||
mem_ref_n |
||
mem_we_n |
||
avl interface |
||
avl_size |
Avalom-MM Slave |
Avalon-MM interface between memory interface and user logic. |
avl_wdata |
||
avl_rdata_valid |
||
avl_rdata |
||
avl_ready |
||
avl_write_req |
||
avl_read_req |
||
avl_addr |
||
status interface |
||
local_init_done |
Conduit |
Memory interface status signals. |
local_cal_success |
||
local_cal_fail |
||
oct interface |
||
rup (Stratix III/IV, Arria II GZ) |
Conduit |
OCT reference resistor pins for rup/rdn or rzqin. |
rdn (Stratix III/IV, Arria II GZ) |
||
rzq (Stratix V) |
||
pll_sharing interface |
||
pll_mem_clk |
Conduit |
Interface signals for PLL sharing, to connect PLL masters to PLL slaves. This interface is enabled only when you set PLL sharing mode to master or slave. |
pll_write_clk |
||
pll_addr_cmd_clk |
||
pll_locked |
||
pll_avl_clk |
||
pll_config_clk |
||
pll_hr_clk |
||
pll_p2c_read_clk |
||
pll_c2p_write_clk |
||
pll_dr_clk |
||
dll_sharing interface |
||
dll_delayctrl |
Conduit |
DLL sharing interface for connecting DLL masters to DLL slaves. This interface is enabled only when you set DLL sharing mode to master or slave. |
oct_sharing interface |
||
seriesterminationcontrol |
Conduit |
OCT sharing interface for connecting OCT masters to OCT slaves. This interface is enabled only when you set OCT sharing mode to master or slave. |
parallelterminationcontrol |
||
parity_error_interrupt interface |
||
parity_error |
Conduit |
Parity error interrupt conduit for connection to custom control block. This interface is enabled only if you turn on Enable Error Detection Parity. |
user_refresh interface |
||
ref_req |
Conduit |
User refresh interface for connection to custom control block. This interface is enabled only if you turn on Enable User Refresh. |
ref_ba |
||
ref_ack |
||
reserved interface |
||
reserved |
Conduit |
Reserved interface required for certain pin configurations when you select the Nios® II-based sequencer. |
Note to Table:
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