Visible to Intel only — GUID: hco1416491142893
Ixiasoft
Visible to Intel only — GUID: hco1416491142893
Ixiasoft
2.7.4. Deskew Example
Let’s assume an operating frequency of 667 MHz, and the package lengths for the pins reported in the .pin file as follows:
dq[0] = 120 ps dq[1] = 120 ps dq[2] = 100 ps dq[3] = 100 ps dqs = 80 ps dqs_n = 80 ps
The following figure illustrates this example.
When you perform length matching for all the traces in the DQS group, you must take package delays into consideration. Because the package delays of traces A and B are 40 ps longer than the package delays of traces E and F, you would need to make the board traces for E and F 40 ps longer than the board traces for A and B.
A similar methodology would apply to traces C and D, which should be 20 ps longer than the lengths of traces A and B.
The following figure shows this scenario with the length of trace A at 450 ps.
When you enter the board skews into the Board Settings tab of the DDR3 parameter editor, you should calculate the board skew parameters as the sums of board delay and corresponding package delay. If a pin does not have a package delay (such as address and command pins), you should use the board delay only.
The example of the preceding figure shows an ideal case where board skews are perfectly matched. In reality, you should allow plus or minus 10 ps of skew mismatch within a DQS group (DQ/DQS/DM).