Visible to Intel only — GUID: hco1416491696929
Ixiasoft
Visible to Intel only — GUID: hco1416491696929
Ixiasoft
9.2.2. Stratix III and Stratix IV PHY Timing Paths
The following figure shows a block diagram of this input path with some of these paths identified for Stratix IV devices. The output datapath contains a similar set of circuits.
The following table lists the timing paths applicable for an interface between Stratix IV devices and half-rate SDRAM components.
Timing Path |
Circuit Category |
Source |
Destination |
---|---|---|---|
Read Data (1) |
Source‑Synchronous and Calibrated |
Memory DQ, DQS Pins |
DQ Capture Registers in IOE |
Write Data (1) |
Source‑Synchronous and Calibrated |
FPGA DQ, DQS Pins |
Memory DQ, DM, and DQS Pins |
Address and command (1) |
Source‑Synchronous |
FPGA CK/CK# and Addr/Cmd Pins |
Memory Input Pins |
Clock-to-Strobe (1) |
Source‑Synchronous |
FPGA CK/CK# and DQS Output Pins |
Memory Input Pins |
Read Resynchronization (1) |
Calibrated |
IOE Capture Registers |
IOE Alignment and Resynchronization Registers |
Read Resynchronization (1) (4) |
Calibrated |
IOE Capture Registers |
Read FIFO in FPGA Core |
PHY IOE-Core Paths (1) |
Source‑Synchronous |
IOE Half Data Rate Registers and Half‑Rate Resynchronization Clock |
FIFO in FPGA Core |
PHY & Controller Internal Paths (1) |
Internal Clock fMAX |
Core registers |
Core registers |
I/O Toggle Rate (2) |
I/O – Data sheet |
FPGA Output Pin |
Memory Input Pins |
Output Clock Specifications (Jitter, DCD) (3) |
I/O – Data sheet |
FPGA Output Pin |
Memory Input Pins |
Notes to Table:
|