Visible to Intel only — GUID: hco1416491356979
Ixiasoft
Visible to Intel only — GUID: hco1416491356979
Ixiasoft
6.2.3. Termination Schemes
These signals include write data (D), byte write select (BWS), read data (Q), clocks (K, K#, CQ, and CQ#), address and command (WPS and RPS).
Signal Type |
HSTL 15/18 Standard (1) (2) |
FPGA End Discrete Termination |
Memory End Termination |
---|---|---|---|
K/K# Clocks |
Class I R50 CAL |
— |
50-ohm Parallel to VTT |
Write Data |
Class I R50 CAL |
— |
50-ohm Parallel to VTT |
BWS |
Class I R50 CAL |
— |
50-ohm Parallel to VTT |
Address (3) (4) |
Class I Max Current |
— |
50-ohm Parallel to VTT |
WPS, RPS (3) (4) |
Class I Max Current |
— |
50-ohm Parallel to VTT |
CQ/CQ# |
Class I |
50-ohm Parallel to VTT |
ZQ50 |
CQ/CQ# ×36 emulated (5) |
Class I |
50-ohm Parallel to VTT |
ZQ50 |
Read Data (Q) |
Class I |
50-ohm Parallel to VTT |
ZQ50 |
QVLD (6) |
— |
— |
ZQ50 |
Notes to Table:
|
Signal Type |
HSTL 15/18 Standard (1) (2) (3) |
FPGA End Discrete Termination |
Memory End Termination |
---|---|---|---|
K/K# Clocks |
DIFF Class I R50 NO CAL |
— |
Series 50 -ohm Without Calibration |
Write Data |
Class I R50 CAL |
— |
50 -ohmParallel to VTT |
BWS |
Class I R50 CAL |
— |
50 -ohmParallel to VTT |
Address (4) (5) |
Class I Max Current |
— |
50 -ohmParallel to VTT |
WPS, RPS (4) (5) |
Class I Max Current |
— |
50 -ohmParallel to VTT |
CQ/CQ# |
Class I P50 CAL |
— |
ZQ50 |
CQ/CQ# ×36 emulated (6) |
— |
50 -ohm Parallel to VTT |
ZQ50 |
Read Data (Q) |
Class I P50 CAL |
— |
ZQ50 |
QVLD (7) |
Class I P50 CAL |
— |
ZQ50 |
Notes to Table:
|
For a ×36 QDR II SRAM interface that uses an emulated mode of two ×18 DQS groups in the FPGA, there are two CQ/CQ# connections at the FPGA and a single CQ/CQ# output from the QDR II SRAM device. Intel recommends that you use a balanced T topology with the trace split close to the FPGA and a parallel termination at the split, as shown in the following figure.
For more information about ×36 emulated modes, refer to the “Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II GX, Stratix III, and Stratix IV Devices" section in the Planning Pin and Resources chapter.