External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Public
Document Table of Contents

5.7.1. Arria V and Stratix V Board Setting Parameters

The following guidelines apply to the Board Setting parameters for Arria V and Stratix V devices.

Setup and Hold Derating

For information on calculating derating parameters, refer to Implementing and Parameterizing Memory IP, in the External Memory Interface Handbook.

Channel Signal Integrity

For information on determining channel signal integrity for Stratix V and earlier products, refer to the wiki page: https://community.intel.com/t5/FPGA-Wiki/Measuring-Channel-Signal-Integrity/ta-p/735495 .

Board Skew

For information on calculating board skew parameters, refer to Implementing and Parameterizing Memory IP, in the External Memory Interface Handbook.

The Board Skew Parameter Tool is an interactive tool that can help you calculate board skew parameters if you know the absolute delay values for all the memory related traces.

Memory Timing Parameters

For information on the memory timing parameters to be entered into the parameter editor, refer to the datasheet for your external memory device.