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Ixiasoft
Visible to Intel only — GUID: hco1416491435433
Ixiasoft
7.2.3.7. Memory Timing Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP
Use the Memory Timing tab to apply the memory timings from your memory manufacturer’s data sheet.
Parameter |
Description |
---|---|
RLDRAM II |
|
Maximum memory clock frequency |
The maximum frequency at which the memory device can run. Set according to memory speed grade. Refer to memory data sheet. |
Refresh interval |
The refresh interval. Set according to memory speed grade. Refer to memory data sheet. |
tCKH (%) |
The input clock (CK/CK#) high expressed as a percentage of the full clock period. Set according to memory speed grade. Refer to memory data sheet. |
tQKH (%) |
The read clock (QK/QK#) high expressed as a percentage of tCKH. Set according to memory speed grade. Refer to memory data sheet. |
tAS |
Address and control setup to CK clock rise. Set according to memory speed grade. Refer to memory data sheet. |
tAH |
Address and control hold after CK clock rise. Set according to memory speed grade. Refer to memory data sheet. |
tDS |
Data setup to clock (CK/CK#) rise. Set according to memory speed grade. Refer to memory data sheet. |
tDH |
Data hold after clock (CK/CK#) rise. Set according to memory speed grade. Refer to memory data sheet. |
tQKQ_max |
QK clock edge to DQ data edge (in same group). Set according to memory speed grade. Refer to memory data sheet. |
tQKQ_min |
QK clock edge to DQ data edge (in same group). Set according to memory speed grade. Refer to memory data sheet. |
tCKDK_max |
Clock to input data clock (max). Set according to memory speed grade. Refer to memory data sheet. |
tCKDK_min |
Clock to input data clock (min). Set according to memory speed grade. Refer to memory data sheet. |