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Ixiasoft
7.2.3.6. Memory Timing Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP
Use the Memory Timing tab to apply the memory timings from your memory manufacturer’s data sheet.
Parameter |
Description |
---|---|
QDR II and QDR II+ SRAM |
|
tWL (cycles) |
The write latency. Set write latency 0 for burst length of 2, and set write latency to 1 for burst length of 4. |
tRL (cycles) |
The read latency. Set according to memory protocol. Refer to memory data sheet. |
tSA |
The address and control setup to K clock rise. Set according to memory protocol. Refer to memory data sheet. |
tHA |
The address and control hold after K clock rise. Set according to memory protocol. Refer to memory data sheet. |
tSD |
The data setup to clock (K/K#) rise. Set according to memory protocol. Refer to memory data sheet. |
tHD |
The data hold after clock (K/K#) rise. Set according to memory protocol. Refer to memory data sheet. |
tCQD |
Echo clock high to data valid. Set according to memory protocol. Refer to memory data sheet. |
tCQDOH |
Echo clock high to data invalid. Set according to memory protocol. Refer to memory data sheet. |
Internal jitter |
The QDRII/II+ internal jitter. Refer to memory data sheet. |
TCQHCQnH |
The CQ clock rise to CQn clock rise (rising edge to rising edge). Set according to memory speed grade. Refer to memory data sheet. |
TKHKnH |
The K clock rise to Kn clock rise (rising edge to rising edge). Set according to memory speed grade. Refer to memory data sheet. |