Visible to Intel only — GUID: hco1416491718929
Ixiasoft
Visible to Intel only — GUID: hco1416491718929
Ixiasoft
9.4.1.4. Read Capture and Write
Read capture and write timing analysis for Arria II, Cyclone IV, Stratix IV, and Stratix V memory interface designs are based on the timing slacks obtained from the Timing Analyzer and all the effects included with the Quartus Prime timing model such as die-to-die and within-die variations, aging, systematic skew, and operating condition variations. Because the PHY IP adjusts the timing slacks to account for the calibration effects, there are two sets of read capture and write timing analysis numbers—Before Calibration and After Calibration.